The present invention relates generally to capacitive sensors, and more particularly to an improved sensor device whose principal use is as a fingerprint sensor.
A capacitive distance sensor is disclosed in commonly assigned U.S. Pat. No. 6,114,862 by Tartagni et al., the relevant portions of the disclosure of which are incorporated herein by reference. The Tartagni patent discloses the basic structure and operation of a conventional solid-state fingerprint sensor that is formed on a single semiconductor chip. FIGS. 1 and 2 herein are simplified schematic views generally corresponding to FIGS. 1 and 4 of the Tartagni patent. The present invention provides an improvement over the structure disclosed in the Tartagni patent.
In FIG. 1 a simplified layout of sixteen sensor elements or pixels conveys the concept of the system architecture of the sensor device, which is designated generally by reference numeral 10, it being understood that many more pixels are employed in practice. For example, STMicroelectronics, Inc. manufactures and markets fingerprint sensors under the brand TouchChip®, which includes Model TCS2CF having 208×288 pixels and Model TCS1CD having 256×360 pixels.
These TouchChip® fingerprint sensors employ an active capacitive pixel-sensing technology, the fundamental aspects of which are disclosed in the Tartagni patent and conceptually reproduced herein in FIGS. 1 and 2. Each of these TouchChip® models employs an array pitch of 50 microns in which a space of 50×50 microns is allocated to each pixel providing an image resolution of 508 dots/inch (DPI) in both X and Y directions. The smaller Model TCS2CF sensor has a sensor surface size of 10.4×14.4 mm, and is designed for integration into portable electronic devices, such as laptop or notebook computers. The larger Model TCS1CD sensor has a sensor surface size of 18.0×12.8 mm, and is designed for integration into various computer and security systems that can accommodate its slightly larger size and usefully employ a larger fingerprint image.
With reference again to FIG. 1, the sensor device 10 includes sensor elements or pixels, some of which are designated by reference numeral 12, arranged in a two-dimensional array A of X rows and Y columns. As noted above in describing the TCS2CF and TCS1CD TouchChip® fingerprint sensors, typically there are more rows than columns. A horizontal scanning stage 14 and a vertical scanning stage 16 are provided for addressing one pixel 12 at a time according to a predetermined scanning sequence. Control lines 18 from the scanning stages 14 and 16 are shown partially for clarity of illustration, but will be understood to run through the array to access each of the pixels 12.
The sensor device 10 also includes a supply and logic unit 20, which supplies power to the circuit elements of the device (including the pixels 12), controls the stages 14 and 16 for sending signals to the pixels 12, and provides timing for various device operations. The unit 20 also sends a reference voltage pulse out on line 22, which is connected to lines 24 running vertically through the array A to each of the pixels 12. In a timed sequence in response to control signals from the scanning stages 14 and 16, the pixels 12 provide output signals on lines 26, which are connected to a common line 28 running from the unit 20 to a buffer 30. The buffer 30 is connected to an analog-to-digital (A/D) converter 32, which sends digital signals representing the values of the pixel output signals to output logic circuitry 34. The output logic circuitry 34 has an output terminal 36 for sending data to a system processor (not shown) for fingerprint verification or imaging depending on the particular application.
FIG. 2 schematically shows two adjacent pixels 12, which are separately designed as pixel 12A and pixel 12B. A skin surface portion 38 of a human finger is depicted over the two pixels with a fingerprint ridge 40 over pixel 12A and a fingerprint valley 42 over pixel 12B. A dielectric layer 44, which is provided atop the array of pixels, has an upper surface 46 that defines a sensing surface to which the fingerprint-bearing skin of a user's finger is applied in a sensing operation. It will be appreciated that fingerprint ridges like the ridge 40 will directly contact the sensing surface 46, and that fingerprint valleys like the valley 42 will be located just above the sensing surface 46. Preferably, a grounded surface grid 48 is provided in the dielectric layer 44 running periodically through the array between rows and columns of pixels. This feature provides a constant reference voltage at the sensing surface 46. The grounded surface grid 48 can also be connected to an electrostatic discharge (ESD) protection circuit (not shown).
Each pixel, of which pixels 12A and 12B are representative, includes first and second coplanar capacitor plates 50 and 52 embedded in the dielectric layer 44 just beneath the sensing surface 46. One possible layout of the plates 50 and 52 is shown in FIG. 1, in which each pixel 12 has rectangular shaped plates 50 and 52 arranged side by side. Connected to the plates 50 and 52 of each pixel 12A and 12B is a sensor circuit 54, which is shown as a generalize circuit block in FIG. 3. As seen in FIG. 2, each sensor circuit 54 includes an inverting amplifier I connected across the plates 50 and 52. A reference voltage pulse Vr is applied through a row select switch T1 and an input capacitor Ci to the input of the inverting amplifier I. A reset switch T2 is connected across the plates 50 and 52 of each pixel and in parallel with the inverting amplifier I. A reset signal R from the supply and logic unit 20, which may be applied through the horizontal scanning stage 14, controls the state of the reset switch T2. Parasitic capacitances are present in the sensor circuit 54 but are not expressly shown. The output of each inverting amplifier I is connected to a pixel output Vout through column select switch T3.
Referring collectively to FIGS. 1-3, the sensor device 10 operates as follows. With the fingerprint-bearing skin 38 of a user's finger in contact with the sensing surface 46, the supply and logic unit 20 begins sequentially addressing individual pixels 12. The reset switches T2 of each pixel 12 are normally closed so that each inverting amplifier I begins a sensing operation at its logical threshold voltage. Just before each pixel 12 is addressed, its reset switch T2 is opened. A row select RS signal is applied by the horizontal scanning stage 14 to each row sequentially, thus closing the row select switches T1 in the selected row. A column select CS signal is also applied by the vertical scanning stage 16 to each column sequentially, thus closing the column select switches T3 in the selected column. After a selected pixel 12 has been addressed in this manner, the reference voltage pulse Vr is applied causing the inverting amplifier I of the selected pixel 12 to generate an output signal Vout that is a function of the capacitance sensed by the plates 50 and 52, which varies with the proximity of the fingerprint-bearing skin 38 of the user's finger above the sensing surface 46 at the site of the selected pixel 12. Sequential addressing continues until each pixel's output Vout has been read out, converted to a digital value by the A/D converter 32, and then transmitted to the output logic circuitry 36, which may include a memory (not shown) for storing the pixel data.
Now referring to FIG. 4, a cross-section of a portion of an integrated circuit (IC) chip 60 is shown schematically to illustrate typical structures that can be used to fabricate transistors and conductors that form the circuitry of a sensor device. The IC chip 60 can be fabricated using conventional complementary metal-oxide-semiconductor (CMOS) processing technology that permits integration of both NMOS and PMOS transistors on the same chip. FIG. 4 shows how the reset switch T2 of FIG. 2 could be implemented as an NMOS transistor and connected to capacitor plates 50 and 52 located above in dielectric layer 44.
The chip 60 may be fabricated on a low resistivity P-type substrate 62, which is preferably monocrystalline silicon. Grown atop and considered to be part of the substrate 62 is an epitaxial layer 64, which is initially high resistivity P-type and is selectively doped during fabrication to form various regions that define circuit elements within the chip 60. At the upper surface of the epitaxial layer 64 are heavily doped N-type source and drain regions 66 and 68 of NMOS transistor T2. The regions 66 and 68 are formed within a P well 70 that has an upper surface portion that defines the channel of transistor T2, a conventional gate structure being formed thereover. A PMOS transistor (not shown) can be formed in an N well 72 partially shown at the broken-off right edge of FIG. 4. The gate structure of transistor T2 includes a gate oxide layer 74, a silicided polysilicon gate 76 and oxide sidewall spacers 78. Such structures and methods for their fabrication are well known.
A composite interconnect structure of conductive and insulating layers is built up in successive steps atop the substrate 62. The composite interconnect structure includes the capacitor plates 50 and 52 imbedded in the dielectric layer 44, the gate structure of transistor T2, and the layers therebetween and surrounding transistor T2 that encompass all of the other circuit elements of the chip 60. A thick oxide layer 80, which is formed atop the epitaxial layer 64, has openings therein that define isolated active areas within which the regions of circuit elements, such as the source and drain regions 66 and 68 of transistor T2, are formed.
A dielectric layer 82 overlies the thick oxide layer 80 and the isolated active areas defined in the openings therein, including the regions 66 and 68 of transistor T2 and the gate structure therebetween. The dielectric layer 82 is preferably a doped oxide such as borophosphosilicate glass (BPSG). A first metalization layer, which preferably primarily comprises aluminum, defines conductive interconnects 84 and 86, which include contacts 88 that extend through etched openings in the dielectric layer 82 to contact the source and drain regions 66 and 68 of transistor T2. Other circuit elements of the chip 60 are interconnected by portions of the first metalization layer in like manner.
A planarized dielectric layer 90 covers the metal interconnects 84 and 86 and the portion of BPSG layer 82 that overlies the gate structure of transistors T2. Preferably, dielectric layer 90 is a composite of a lower undoped oxide, an intermediate spin-on-glass (SOG), and an upper undoped oxide, which are not shown separately. According to well-known processing techniques, the intermediate SOG portion of the composite dielectric layer 90 is used to planarize the structure.
The process continues by etching via openings through the dielectric layer 90 down to the conductive interconnects therebelow, and then performing a second metalization deposition of aluminum, which is patterned to form the plates 50 and 52 and includes metal vias 92 that connect the plates to the underlying conductive interconnects 84 and 86. Then, the dielectric layer 44 is formed, preferably by successive deposition steps that produce a composite multilayer structure that includes a hydrogen silesquioxane (HSG) portion between the plates 50 and 52, a thin intermediate portion of phosphosilicate glass (PSG) atop the HSQ and the plates 50 and 52, a second intermediate portion of silicon nitride atop the PSG, and an outer portion of silicon carbide atop the silicon nitride. These multilayer portions of dielectric layer 44 are not separately delineated in FIG. 4, but techniques for their fabrication are well known. It will be appreciated by those skilled in the art that the outer portion of silicon carbide provides a hard, scratch-resistant sensing surface 46.
The layout chosen for the plates 50 and 52 affects the sensitivity of the pixels. This fact is recognized by the Tartagni patent, which discloses in FIGS. 8-12 several different plate patterns as alternatives to two side-by-side rectangular plates. The various different plate patterns disclosed by the Tartagni patent have different sensitivities, which is a function of both the direct capacitance and fringing capacitance of the particular plate pattern. The direct capacitance of each plate is a function of its area and its proximity to the object being sensed. The fringing capacitance of two side-by-side plates is a function of the total perimeter length of adjacent faces or edges of the plates and their proximity to the object being sensed. The total feedback capacitance experienced by the inverting amplifier I is a function of the direct capacitances between the plates and the object being sensed, and of the fringing capacitance, which is modulated by the object being sensed.
The present invention provides an improved sensor device that can be fabricated using conventional CMOS processing techniques similar to those described above. Regardless of the particular plate pattern chosen, whether it is one of the five specific patterns shown in FIGS. 8-12 of U.S. Pat. No. 6,114,862 or a further variation thereof, each pixel output has an accuracy that depends to an extent on the particular plate pattern. However, it will be appreciated that the particular plate pattern is a permanent feature of a sensor device constructed according to the teachings of the Tartagni patent. The present invention recognizes and addresses this problem.